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Datasheet File OCR Text:

M50FLW040A M50FLW040B
4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
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FLASH MEMORY - Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used in PC BIOS applications - 5 Signal Communication Interface supporting Read and Write Operations - 5 Additional General Purpose Inputs for platform design flexibility - Synchronized with 33MHz PCI clock 8 BLOCKS OF 64 KBYTES - 5 blocks of 64 KBytes each - 3 blocks, subdivided into 16 uniform sectors of 4 KBytes each Two blocks at the top and one at the bottom (M50FLW040A) One block at the top and two at the bottom (M50FLW040B) ENHANCED SECURITY - Hardware Write Protect Pins for Block Protection - Register-based Read and Write Protection SUPPLY VOLTAGE - VCC = 3 to 3.6V for Program, Erase and Read Operations - VPP = 12V for Fast Program and Erase TWO INTERFACES - Auto Detection of Firmware Hub (FWH) or Low Pin Count (LPC) Memory Cycles for Embedded Operation with PC Chipsets - Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility. PROGRAMMING TIME: 10s typical PROGRAM/ERASE CONTROLLER - Embedded Program and Erase algorithms - Status Register Bits
Figure 1. Packages
PLCC32 (K)
TSOP32 (NB) 8 x 14mm
TSOP40 (N) 10 x 20mm
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PROGRAM/ERASE SUSPEND - Read other Blocks/Sectors during Program Suspend - Program other Blocks/Sectors during Erase Suspend ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code (M50FLW040A): 08h - Device Code (M50FLW040B): 28h
August 2004
1/52
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M50FLW040A, M50FLW040B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Figure 3. Table 1. Table 2. Figure 4. Figure 5. Figure 6. Table 3. Table 4. Logic Diagram (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Addresses (M50FLW040A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Addresses (M50FLW040B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 10 Input/Output Communications (FWH0/LAD0-FWH3/LAD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Communication Frame (FWH4/LFRAME). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Identification Inputs (ID0-ID3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . . 12 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. LPC Bus Write Field Definitions (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 12. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Quadruple Byte Program Command (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Double/Quadruple Byte Program Command (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program/Erase Controller Status (Bit SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Suspend Status (Bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VPP Status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Suspend Status (Bit SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . . 24 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 15. Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . . 25 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 19. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 20. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 21. FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 22. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 23. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 24. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 25. FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 15.FWH/LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 26. FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 27. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 17.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 28. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 18.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 29. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 19.PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 36 Table 30. PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 37 Figure 20.TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 38 Table 31. TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 38 Figure 21.TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 39
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Table 32. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 39 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 34. M50FLW040A Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 35. M50FLW040B Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . . 45 Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 46 Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 47 Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 48 Figure 27.Sector/Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 50 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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M50FLW040A, M50FLW040B
SUMMARY DESCRIPTION
The M50FLW040 is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines, an optional 12V power supply can be used to reduce the erasing and programming time. The memory is divided into 8 Uniform Blocks of 64 KBytes each, three of which are divided into 16 uniform sectors of 4 KBytes each (see APPENDIX A. for details). All blocks and sectors can be erased independently. So, it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents. Program and erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set to control the memory is consistent with the JEDEC standards. Two different bus interfaces are supported by the memory: s The primary interface, the FWH/LPC Interface, uses Intel's proprietary Firmware Hub (FWH) and Low Pin Count (LPC) protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets. The M50FLW040 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. s The secondary interface, the Address/ Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production line programming prior to fitting the device in a PC Motherboard. The memory is supplied with all the bits erased (set to '1').
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M50FLW040A, M50FLW040B
Figure 2. Logic Diagram (FWH/LPC Interface)
VCC VPP 4 ID0-ID31 5 GPI0GPI4 FWH4/LFRAME CLK IC RP INIT
RFU VCC
AI08417B
Table 1. Signal Names (FWH/LPC Interface)
FWH0/LAD0FWH3/LAD3 FWH4/ LFRAME ID0-ID3 Input/Output Communications Input Communication Frame Identification Inputs General Purpose Inputs Interface Configuration Interface Reset CPU Reset Clock Top Block Lock Write Protect Reserved for Future Use. Leave disconnected Supply Voltage Optional Supply Voltage for Fast Program and Erase Operations Ground Not Connected Internally
4 FWH0/LAD0 FWH3/LAD3 WP M50FLW040A M50FLW040B TBL
GPI0-GPI4 IC RP INIT CLK TBL WP
VSS
VPP VSS NC
Note: 1. ID3 is Reserved for Future Use (RFU) in LPC mode.
Figure 3. Logic Diagram (A/A Mux Interface)
Table 2. Signal Names (A/A Mux Interface)
VCC VPP 11 A0-A10 8 DQ0-DQ7
IC A0-A10 DQ0-DQ7 G W RC Interface Configuration Address Inputs Data Inputs/Outputs Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast Program and Erase Operations Ground Not Connected Internally
RC IC G W RP
VSS NC
M50FLW040A M50FLW040B
RB
RB
RP VCC VPP
VSS
AI08418B
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M50FLW040A, M50FLW040B
Figure 4. PLCC Connections
A8 A9 RP VPP VCC RC A10
A/A Mux
A/A Mux
A7 A6 A5 A4 A3 A2 A1 A0
GPI2 GPI3 RP VPP VCC CLK GPI4
1 32 GPI1 GPI0 WP TBL ID3/RFU ID2 ID1 ID0 IC (VIL) NC NC VSS VCC INIT FWH4/LFRAME RFU RFU IC (VIH) NC NC VSS VCC G W RB DQ7
9
M50FLW040A M50FLW040B
25
DQ0 FWH0/LAD0 17
DQ1 FWH1/LAD1 DQ2 FWH2/LAD2 VSS VSS DQ3 FWH3/LAD3 DQ4 RFU DQ5 RFU DQ6 RFU
A/A Mux
A/A Mux
AI08419B
Note: Pins 27 and 28 are not internally connected.
Figure 5. TSOP32 Connections
NC NC NC NC IC (VIH) A10 RC VCC VPP RP A9 A8 A7 A6 A5 A4 A/A Mux
NC NC NC VSS IC GPI4 CLK VCC VPP RP GPI3 GPI2 GPI1 GPI0 WP TBL
1
32
INIT FWH4/LFRAME NC RFU RFU RFU RFU FWH3/LAD3 VSS FWH2/LAD2 FWH1/LAD1 FWH0/LAD0 ID0 ID1 ID2 ID3/RFU
G W NC DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
A/A Mux
8 9
M50FLW040A 25 M50FLW040B 24
16
17
AI09742B
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M50FLW040A, M50FLW040B
Figure 6. TSOP40 Connections
NC IC (VIH) NC NC NC NC A10 NC RC VCC VPP RP NC NC A9 A8 A7 A6 A5 A4
NC IC (VIL) NC NC NC NC GPI4 NC CLK VCC VPP RP NC NC GPI3 GPI2 GPI1 GPI0 WP TBL
1
40
10 M50FLW040A 31 11 M50FLW040B 30
20
21
VSS VCC FWH4/LFRAME INIT RFU RFU RFU RFU RFU VCC VSS VSS FWH3/LAD3 FWH2/LAD2 FWH1/LAD1 FWH0/LAD0 ID0 ID1 ID2 ID3/RFU
VSS VCC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
A/A Mux
A/A Mux
AI08420B
Table 3. Addresses (M50FLW040A)
Block Size Address Range (KByte) 64 64 64 64 64 64 64 64 70000h-7FFFFh 60000h-6FFFFh 50000h- 5FFFFh 40000h- 4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh 16 x 4KBytes 5 x 64KBytes Sector Size (KByte) 16 x 4KBytes 16 x 4KBytes
Table 4. Addresses (M50FLW040B)
Block Size Address Range (KByte) 64 64 64 64 64 64 64 64 70000h-7FFFFh 60000h- 6FFFFh 50000h- 5FFFFh 40000h- 4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh 16 x 4KBytes 16 x 4KBytes 5 x 64KBytes Sector Size (KByte) 16 x 4KBytes
Note: Also see APPENDIX A., Table 34. and Table 35. for a full listing of the Block Addresses.
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M50FLW040A, M50FLW040B
SIGNAL DESCRIPTIONS
There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions section, respectively, while the supply signals are discussed in the Supply Signal Descriptions section. Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions Please see Figure 2. and Table 1.. Input/Output Communications (FWH0/LAD0FWH3/LAD3). All Input and Output Communications with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins. Input Communication Frame (FWH4/ LFRAME). The Input Communication Frame (FWH4/LFRAME) signal indicates the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock, a new bus operation is initiated. If Input Communication Frame is Low, V IL, during a bus operation then the operation is aborted. When Input Communication Frame is High, V IH, the current bus operation is either proceeding or the bus is idle. Identification Inputs (ID0-ID3). Up to 16 memories can be addressed on a bus, in the Firmware Hub (FWH) mode. The Identification Inputs allow each device to be given a unique 4-bit address. A `0' is signified on a pin by driving it Low, VIL, or leaving it floating (since there is an internal pulldown resistor, with a value of R IL). A `1' is signified on a pin by driving it High, V IH (and there will be a leakage current of ILI2 through the pin). By convention, the boot memory must have address `0000', and all additional memories are given addresses, allocated sequentially, from `0001'. In the Low Pin Count (LPC) mode, the identification Inputs (ID0-ID2) can address up to 8 memories on a bus. In the LPC mode, the ID3 pin is Reserved for Future Use (RFU). The value on address A19-A21 is compared to the hardware strapping on the ID0-ID2 pins to select the memory that is being addressed. For an address bit to be `1', the corresponding ID pin can be left floating or driven Low, V IL (again, with the internal pull-down resistor, with a value of RIL). For an address bit to be `0', the corresponding ID pin must be driven High, VIH (and there will be a leakage current of ILI2 through the pin, as specified in Table 24.). For details, see Table 5.. General Purpose Inputs (GPI0-GPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read, with their contents being available in the General Purpose Inputs Register. The pins must have stable data throughout the entire cycle that reads the General Purpose Input Register. These pins should be driven Low, VIL, or High, V IH, and must not be left floating. Interface Configuration (IC). The Interface Configuration input selects whether the FWH/LPC interface or the Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface Configuration, IC, should not be changed during operation of the memory device, except for selecting the desired interface in the period before power-up or during a Reset. To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or driven Low, VIL. To select the Address/Address Multiplexed (A/A Mux) Interface, the pin should be driven High, VIH. An internal pull-down resistor is included with a value of R IL; there will be a leakage current of ILI2 through each pin when pulled to VIH. Interface Reset (RP). The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is driven Low, VIL, the memory is in Reset mode (the outputs go to high impedance, and the current consumption is minimized). When RP is driven High, VIH, the device is in normal operation. After exiting Reset mode, the memory enters Read mode. CPU Reset (INIT). The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI specification. Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL, is driven Low, V IL, program and erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is driven High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 6). For details, see APPENDIX A.. Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and must not be changed until the operation has completed, otherwise unpredictable results may occur. Similarly, unpredictable behavior is possible if WP is
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M50FLW040A, M50FLW040B
changed during Program or Erase Suspend, and care should be taken to avoid this. Write Protect (WP). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being changed. When Write Protect, WP, is driven Low, V IL, Program and Erase operations in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is driven High, V IH, the protection of the Block is determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 7). For details, see APPENDIX A.. Write Protect, WP, must be set prior to a Program or Erase operation is initiated, and must not be changed until the operation has completed otherwise unpredictable results may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or Erase Suspend, and care should be taken to avoid this. Reserved for Future Use (RFU). These pins do not presently have assigned functions. They must be left disconnected, except for ID3 (when in LPC mode) which can be left connected. The electrical characteristics for this signal are as described in the "Identification Inputs (ID0-ID3)." section. Address/Address Multiplexed (A/A Mux) Signal Descriptions Please see Figure 3. and Table 2.. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A18). They are latched during any bus operation by the Row/Column Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is to be written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they carry the commands that are sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable signal, G, controls the output buffers during a Bus Read operation. Write Enable (W). The Write Enable signal, W, controls the Bus Write operation of the Command Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs are to be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on its rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the device's Program/Erase Controller. When Ready/Busy is Low, V OL, the device is busy with a program or erase operation, and it will not accept any additional program or erase command (except for the Program/Erase Suspend command). When Ready/Busy is High, VOH, the memory is ready for any read, program or erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfaces. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (read, program, erase, etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This is to prevent Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time, the operation aborts, and the memory contents that were being altered will be invalid. After VCC becomes valid, the Command Interface is reset to Read mode. A 0.1F capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both V CC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program command description in A/A Mux interface and the Double/ Quadruple Byte Program command description in FWH mode) and Fast Erase options of the memory. When VPP = VCC, program and erase operations take place as normal. When VPP = VPPH, Fast Program and Erase operations are used. Any other voltage input to VPP will result in undefined behavior, and should not be used. VPP should not be set to VPPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the voltage measurements.
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M50FLW040A, M50FLW040B
Table 5. Memory Identification Input Configuration (LPC mode)
Memory Number 1 (Boot memory) 2 3 4 5 6 7 8 ID2 VIL or float VIL or float VIL or float VIL or float VIH VIH VIH VIH ID1 VIL or float VIL or float VIH VIH VIL or float VIL or float VIH VIH ID0 VIL or float VIH VIL or float VIH VIL or float VIH VIL or float VIH A21 1 1 1 1 0 0 0 0 A20 1 1 0 0 1 1 0 0 A19 1 0 1 0 1 0 1 0
BUS OPERATIONS
The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with different bus signals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full functionality, while the Address/Address Multiplexed (A/A Mux) Interface is orientated for erase and program operations. See the sections below, The Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations and Address/Address Multiplexed (A/A Mux) Bus Operations, for details of the bus operations on each interface. Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations The M50FLW040 automatically identifies the type of FWH/LPC protocol from the first received nibble (START nibble) and decodes the data that it receives afterwards, according to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface consists of four data signals (FWH0/LAD0-FWH3/LAD3), one control line (FWH4/LFRAME) and a clock (CLK). Protection against accidental or malicious data corruption is achieved using two additional signals (TBL and WP). And two reset signals (RP and INIT) are available to put the memory into a known state. The data, control and clock signals are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds of up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. Bus Read. Bus Read operations are used to read from the memory cells, specific registers in the Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Read operation starts on the rising edge of the Clock signal when the Input Communication Frame, FWH4/ LFRAME, is Low, V IL, and the correct Start cycle is present on FWH0/LAD0-FWH3/LAD3. On subsequent clock cycles the Host will send to the memory: s ID Select, Address and other control bits on FWH0-FWH3 in FWH mode. s Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode. The device responds by outputting Sync data until the wait states have elapsed, followed by Data0Data3 and Data4-Data7. See Table 6. and Table 8., and Figure 7. and Figure 9., for a description of the Field definitions for each clock cycle of the transfer. See Table 26., and Figure 15., for details on the timings of the signals. Bus Write. Bus Write operations are used to write to the Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Write operation starts on the rising edge of the Clock signal when Input Communication Frame, FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0-FWH3/LAD3. On subsequent Clock cycles the Host will send to the memory: s ID Select, Address, other control bits, Data0Data3 and Data4-Data7 on FWH0-FWH3 in FWH mode. s Cycle Type + Dir, Address, other control bits, Data0-Data3 and Data4-Data7 on LAD0LAD3. The device responds by outputting Sync data until the wait states have elapsed.
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M50FLW040A, M50FLW040B
See Table 7. and Table 9., and Figure 8. and Figure 10., for a description of the Field definitions for each clock cycle of the transfer. See Table 26., and Figure 15., for details on the timings of the signals. Bus Abort. The Bus Abort operation can be used to abort the current bus operation immediately. A Bus Abort occurs when FWH4/LFRAME is driven Low, VIL, during the bus operation. The device puts the Input/Output Communication pins, FWH0/LAD0-FWH3/LAD3, to high impedance. Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received. A Bus Abort during the final TAR cycles is not guaranteed to abort the command. The bus, however, will be released immediately. Standby. When FWH4/LFRAME is High, VIH, the device is put into Standby mode, where FWH0/ LAD0-FWH3/LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. Reset. During the Reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put to high-impedance. The device is in the Reset mode when Interface Reset, RP, or CPU Reset, INIT, is driven Low, V IL. RP or INIT must be held Low, V IL, for tPLPH. The memory reverts to the Read mode upon return from the Reset mode, and the Lock Registers return to their default states regardless of their states before Reset. If RP or INIT goes Low, V IL, during a Program or Erase operation, the operation is aborted and the affected memory cells no longer contain valid data. The device can take up to tPLRH to abort a Program or Erase operation. Block Protection. Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. Address/Address Multiplexed (A/A Mux) Bus Operations The Address/Address Multiplexed (A/A Mux) Interface has a more traditional-style interface. The signals consist of a multiplexed address signals (A0A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH)/Low Pin Count (LPC) Interface are available; these include all the Commands but exclude the Security features and other registers. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset. When the Address/Address Multiplexed (A/A Mux) Interface is selected, all the blocks are unprotected. It is not possible to protect any blocks through this interface. Bus Read. Bus Read operations are used to read the contents of the Memory Array, the Electronic Signature or the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. Write Enable (W) and Interface Reset (RP) must be High, VIH, and Output Enable, G, Low, VIL. The Data Inputs/Outputs will output the value, according to the timing constraints specified in Figure 17., and Table 28.. Bus Write. Bus Write operations are used to write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH; and Write Enable, W, must be Low, VIL. The Data Inputs/ Outputs are latched on the rising edge of Write Enable, W. See Figure 18., and Table 29., for details of the timing requirements. Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH. Reset. During the Reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put at high-impedance. The device is in the Reset mode when RP is Low, VIL. RP must be held Low, V IL for tPLPH. If RP goes Low, VIL, during a Program or Erase operation, the operation is aborted, and the affected memory cells no longer contain valid data. The memory can take up to tPLRH to abort a Program or Erase operation.
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M50FLW040A, M50FLW040B
Table 6. FWH Bus Read Field Definitions
Clock Cycle Number 1 Clock Cycle Count 1 Field FWH0- Memory FWH3 I/O 1101b I Description On the rising edge of CLK with FWH4 Low, the contents of FWH0FWH3 indicate the start of a FWH Read cycle. Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. A 28-bit address is transferred, with the most significant nibble first. For the multi-byte read operation, the least significant bits (MSIZE of them) are treated as Don't Care, and the read operation is started with each of these bits reset to 0. Address lines A19-21 and A23-27 are treated as Don't Care during a normal memory array access, with A22=1, but are taken into account for a register access, with A22=0. (See Table 15.) This one clock cycle is driven by the host to determine the number of Bytes that will be transferred. M50FLW040 supports: single Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer (0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b). The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle. Data transfer is two CLK cycles, starting with the least significant nibble. If multi-Byte read operation is enabled, repeat cycle-16 and cycle-17 n times, where n = 2MSIZE. The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3.
START
2
1
IDSEL
XXXX
I
3-9
7
ADDR
XXXX
I
10
1
MSIZE
XXXX
I
11 12
1 1
TAR TAR
1111b 1111b (float) 0101b
I O
13-14
2
WSYNC
O
15
1
RSYNC
0000b
O
16-17 previous +1 previous +1
M=2n
DATA
XXXX
O
1 1
TAR TAR
1111b 1111b (float)
O N/A
Figure 7. FWH Bus Read Waveforms
CLK
FWH4
FWH0-FWH3 Number of clock cycles
START 1
IDSEL 1
ADDR 7
MSIZE 1
TAR 2
SYNC 3
DATA M
TAR 2 AI08433B
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M50FLW040A, M50FLW040B
Table 7. FWH Bus Write Field Definitions
Clock Cycle Number 1 Clock Cycle Count 1 Field FWH0- Memory FWH3 I/O 1110b I Description On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle. Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. A 28-bit address is transferred, with the most significant nibble first. Address lines A19-21 and A23-27 are treated as Don't Care during a normal memory array access, with A22=1, but are taken into account for a register access, with A22=0. (See Table 15.) 0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b (Quadruple Byte Transfer). Data transfer is two cycles, starting with the least significant nibble. (The first pair of nibbles is that at the address with A1A0 set to 00, the second pair with A1-A0 set to 01, the third pair with A1-A0 set to 10, and the fourth pair with A1-A0 set to 11. In Double Byte Program the first pair of nibbles is that at the address with A0 set to 0, the second pair with A0 set to 1) The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b, indicating a turnaround cycle. The FWH Flash Memory floats its outputs and the host takes control of FWH0-FWH3.
START
2
1
IDSEL
XXXX
I
3-9
7
ADDR
XXXX
I
10
1
MSIZE
XXXX
I
11-18
M=2/4/8
DATA
XXXX
I
previous +1 previous +1 previous +1 previous +1 previous +1
1 1 1 1 1
TAR TAR SYNC TAR TAR
1111b 1111b (float) 0000b 1111b 1111b (float)
I O O O N/A
Figure 8. FWH Bus Write Waveforms
CLK
FWH4
FWH0-FWH3 Number of clock cycles
START 1
IDSEL 1
ADDR 7
MSIZE 1
DATA M
TAR 2
SYNC 1
TAR 2 AI08434B
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M50FLW040A, M50FLW040B
Table 8. LPC Bus Read Field Definitions (1-Byte)
Clock Cycle Number Clock Cycle Count 1 Field LAD0LAD3 Memory I/O Description On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. Indicates the type of cycle and selects 1-byte reading. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is Don't Care. A 32-bit address is transferred, with the most significant nibble first. A23-A31 must be set to 1. A22=1 for memory access, and A22=0 for register access. Table 5. shows the appropriate values for A21-A19. The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle. Data transfer is two CLK cycles, starting with the least significant nibble. The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3.
1
START
0000b
I
2
1
CYCTYPE + DIR
0100b
I
3-10
8
ADDR
XXXX
I
11 12
1 1
TAR TAR
1111b 1111b (float)
I O
13-14
2
WSYNC
0101b
O
15
1
RSYNC
0000b
O
16-17 18 19
2 1 1
DATA TAR TAR
XXXX 1111b 1111b (float)
O O N/A
Figure 9. LPC Bus Read Waveforms (1-Byte)
CLK
LFRAME
LAD0-LAD3 Number of clock cycles
START 1
CYCTYPE + DIR 1
ADDR 8
TAR 2
SYNC 3
DATA 2
TAR 2 AI04429
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M50FLW040A, M50FLW040B
Table 9. LPC Bus Write Field Definitions (1 Byte)
Clock Cycle Number 1 Clock Cycle Count 1 Field LAD0LAD3 Memory I/O Description On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 1b for write. Bit 0 is don't care (X). A 32-bit address is transferred, with the most significant nibble first. A23-A31 must be set to 1. A22=1 for memory access, and A22=0 for register access. Table 5. shows the appropriate values for A21-A19. Data transfer is two cycles, starting with the least significant nibble. The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating it has received data or a command. The LPC Flash Memory drives LAD0-LAD3 to 1111b, indicating a turnaround cycle. The LPC Flash Memory floats its outputs and the host takes control of LAD0-LAD3.
START CYCTY PE + DIR
0000b
I
2
1
011Xb
I
3-10
8
ADDR
XXXX
I
11-12 13 14 15 16 17
2 1 1 1 1 1
DATA TAR TAR SYNC TAR TAR
XXXX 1111b 1111b (float) 0000b 1111b 1111b (float)
I I O O O N/A
Figure 10. LPC Bus Write Waveforms (1 Byte)
CLK
LFRAME
LAD0-LAD3 Number of clock cycles
START 1
CYCTYPE + DIR 1
ADDR 8
DATA 2
TAR 2
SYNC 1
TAR 2 AI04430
Table 10. A/A Mux Bus Operations
Operation Bus Read Bus Write Output Disable Reset G VIL VIH VIH VIL or VIH W VIH VIL VIH VIL or VIH RP VIH VIH VIH VIL VPP Don't Care VCC or VPPH Don't Care Don't Care DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z
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M50FLW040A, M50FLW040B
COMMAND INTERFACE
All Bus Write operations to the device are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings, and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface reverts to the Read mode when power is first applied, or when exiting from Reset. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. See Table 11. for the available Command Codes. Table 11. Command Codes
Hexadecimal 10h 20h 32h 40h 50h 70h 80h 90h B0h D0h FFh Command Alternative Program Setup, Double/ Quadruple Byte Program Setup, Chip Erase Confirm Block Erase Setup Sector Erase Setup Program, Double/Quadruple Byte Program Setup Clear Status Register Read Status Register Chip Erase Setup Read Electronic Signature Program/Erase Suspend Program/Erase Resume, Block Erase Confirm, Sector Erase Confirm Read Memory Array
any Read Memory Array commands until the operation has completed. For a multibyte read, in the FWH mode, the address, that was transmitted with the command, will be automatically aligned, according to the MSIZE granularity. For example, if MSIZE=7, regardless of any values that are provided for A6-A0, the first output will be from the location for which A6-A0 are all `0's. Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued, subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued, the Manufacturer Code and Device Code can be read using conventional Bus Read operations, and the addresses shown in Table 12.. Table 12. Electronic Signature Codes
Code Manufacturer Code Device Code M50FLW040A M50FLW040B Address1 ...00000h ...00001h Data 20h 08h 28h
Note: 1. A22 should be `1', and the ID lines and upper address bits should be set according to the rules illustrated in Table 5., Table 6. and Table 8..
The following commands are the basic commands used to read from, write to, and configure the device. The following text descriptions should be read in conjunction with Table 13.. Read Memory Array Command. The Read Memory Array command returns the device to its Read mode, where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the device to Read mode. Once the command is issued, the device remains in Read mode until another command is issued. From Read mode, Bus Read operations access the memory array. If the Program/Erase Controller is executing a Program or Erase operation, the device will not accept
The device remains in this mode until another command is issued. That is, subsequent Bus Read operations continue to read the Manufacturer Code, or the Device Code, and not the Memory Array. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The Program command works by changing appropriate bits from `1' to `0'. (It cannot change a bit from `0' back to `1'. Attempting to do so will not modify the value of the bit. Only the Erase command can set bits back to `1'. and does so for all of the bits in the block.) Two Bus Write operations are required to issue the Program command. The second Bus Write cycle latches the address and data, and starts the Program/Erase Controller.
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M50FLW040A, M50FLW040B
Once the command is issued, subsequent Bus Read operations read the value in the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the address falls in a protected block, the Program operation will abort, the data in the memory array will not be changed, and the Status Register will indicate the error. During the Program operation, the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands are ignored. See Figure 22., for a suggested flowchart on using the Program command. Typical Program times are given in Table 18.. Quadruple Byte Program Command (A/A Mux Interface). The Quadruple Byte Program Command is used to program four adjacent Bytes in the memory array at a time. The four Bytes must differ only for addresses A0 and A1. Programming should not be attempted when V PP is not at V PPH. Five Bus Write operations are required to issue the command. The second, third and fourth Bus Write cycles latch the respective addresses and data of the first, second and third Bytes in the Program/ Erase Controller. The fifth Bus Write cycle latches the address and data of the fourth Byte and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the value in the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) During the Quadruple Byte Program operation, the memory will only accept the Read Status Register and Program/Erase Suspend commands. All other commands are ignored. Note that the Quadruple Byte Program command cannot change a bit set to `0' back to `1' and attempting to do so will not modify its value. One of the erase commands must be used to set all of the bits in the block to `1'. See Figure 24., for a suggested flowchart on using the Quadruple Byte Program command. Typical Quadruple Byte Program times are given in Table 18.. Double/Quadruple Byte Program Command (FWH Mode). The Double/Quadruple Byte Program Command can be used to program two/four adjacent Bytes to the memory array at a time. The two Bytes must differ only for address A0; the four Bytes must differ only for addresses A0 and A1. Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the start address and two/four data Bytes and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) During the Double/Quadruple Byte Program operation the memory will only accept the Read Status register and Program/Erase Suspend commands. All other commands are ignored. Note that the Double/Quadruple Byte Program command cannot change a bit set to `0' back to `1' and attempting to do so will not modify its value. One of the erase commands must be used to set all of the bits in the block to `1'. See Figure 23., for a suggested flowchart on using the Double/Quadruple Byte Program command. Typical Double/Quadruple Byte Program times are given in Table 18.. Chip Erase Command. The Chip Erase Command erases the entire memory array, setting all of the bits to `1'. All previous data in the memory array are lost. This command, though, is only available under the A/A Mux interface. Two Bus Write operations are required to issue the command, and to start the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) Erasing should not be attempted when V PP is not at VPPH, otherwise the result is uncertain. During the Chip Erase operation, the memory will only accept the Read Status Register command. All other commands are ignored. See Figure 26., for a suggested flowchart on using the Chip Erase command. Typical Chip Erase times are given in Table 18.. Block Erase Command. The Block Erase command is used to erase a block, setting all of the bits to `1'. All previous data in the block are lost. Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the block address and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the block is protected (FWH/LPC only) then the Block Erase operation will abort, the data in the block will not be changed, and the Status Register will indicate the error. During the Block Erase operation the memory will only accept the Read Status Register and Program/Erase Suspend commands. All other commands are ignored.
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M50FLW040A, M50FLW040B
See Figure 27., for a suggested flowchart on using the Block Erase command. Typical Block Erase times are given in Table 18.. Sector Erase Command. The Sector Erase command is used to erase a Uniform 4-KByte Sector, setting all of the bits to `1'. All previous data in the sector are lost. Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the Sector address and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the Block to which the Sector belongs is protected (FWH/LPC only) then the Sector Erase operation will abort, the data in the Sector will not be changed, and the Status Register will indicate the error. During the Sector Erase operation the memory will only accept the Read Status Register and Program/Erase Suspend commands. All other commands are ignored. See Figure 27., for a suggested flowchart on using the Sector Erase Command. Typical Sector Erase times are given in Table 18.. Clear Status Register Command. The Clear Status Register command is used to reset Status Register bits SR1, SR3, SR4 and SR5 to `0'. One Bus Write is required to issue the command. Once the command is issued, the device returns to its previous mode, subsequent Bus Read operations continue to output the data from the same area, as before. Once set, these Status Register bits remain set. They do not automatically return to `0', for example, when a new program or erase command is issued. If an error has occurred, it is essential that any error bits in the Status Register are cleared, by issuing the Clear Status Register command, before attempting a new program or erase command. Program/Erase Suspend Command. The Program/Erase Suspend command is used to pause the Program/Erase Controller during a program or Sector/Block Erase operation. One Bus Write cycle is required to issue the command. Once the command has been issued, it is necessary to poll the Program/Erase Controller Status bit until the Program/Erase Controller has paused. No other commands are accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the device continues to output the contents of the Status Register until another command is issued. During the polling period, between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing, it is possible for the operation to complete. Once the Program/Erase Controller Status bit indicates that the Program/ Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. During Program/Erase Suspend, the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Sector Erase or Block Erase then the program command will also be accepted. However, it should be noted that only the Sectors/Blocks not being erased may be read or programmed correctly. See Figure 25., and Figure 28., for suggested flowcharts on using the Program/Erase Suspend command. Typical times and delay durations are given in Table 18.. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the command. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register.
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M50FLW040A, M50FLW040B
Table 13. Commands
Cycle Bus Operations(1) 1st Addr Read Memory Array(2,10,11) Read Status Register(3,10) Read Electronic Signature(10) Program / Multiple Byte program (FWH)(4,9,11) Quadruple Byte Program (A/A Mux)(4,12) Chip Erase(4) Block Erase(4) Sector Erase(4) Clear Status Register(5) Program/Erase suspend(6) Program/Erase resume(7) 1+ 1+ 1+ X X X Data FFh 70h 90h or 98h 40h or 10h 2nd Addr Read Addr X Sig Addr Prog Addr Data Read Data Status Reg Signat ure Prog Data Prog Data1 10h D0h D0h Prog Data2 Prog Data3 Prog Data4 Addr (Read Addr2) (X) (Sig Addr) 3rd Data (Read Data2) (Status Reg) (Signat ure) Addr (Read Addr3) (X) (Sig Addr) 4th Data (Read Data3) (Status Reg) (Signat ure) Addr (Read Addr4) (X) (Sig Addr) 5th Data (Read Data4) (Status Reg) (Signat ure)
Command
2
X
5 2 2 2 1 1 1 1 1
X X X X X X X X X X X X
30h 80h 20h 32h 50h B0h D0h 00h 01h 60h 2Fh C0h
A1 X BA SA
A2
A3
A4
Invalid
reserved(8)
1 1 1
Note: 1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles are WRITE. BA = Any address in the Block, SA = Any address in the Sector. X = Don't Care, except that A22=1 (for FWH or LPC mode), and A21, A20 and A19 are set according to the rules shown in Table 5. (for LPC mode) 2. After a Read Memory Array command, read the memory as normal until another command is issued. 3. After a Read Status Register command, read the Status Register as normal until another command is issued. 4. After the erase and program commands read the Status Register until the command completes and another command is issued. 5. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to `0'. 6. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during Erase Suspend) and Program/Erase Resume commands can be issued. 7. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. 8. Do not use Invalid or Reserved commands. 9. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Dont Care. PD is two or four Bytes depending on Msize code. 10. "1+" indicates that there is one write cycle, followed by any number of read cycles. 11. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation is all that is needed. 12. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
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M50FLW040A, M50FLW040B
STATUS REGISTER
The Status Register provides information on the current or previous Program or Erase operation. The bits in the Status Register convey specific information about the progress of the operation. To read the Status Register, the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address. The text descriptions, below, should be read in conjunction with Table 14., where the meanings of the Status Register bits are summarized. Program/Erase Controller Status (Bit SR7). This bit indicates whether the Program/Erase Controller is active or inactive. When the Program/ Erase Controller Status bit is `0', the Program/ Erase Controller is active; when the bit is `1', the Program/Erase Controller is inactive. The Program/Erase Controller Status is `0' immediately after a Program/Erase Suspend command is issued, until the Program/Erase Controller pauses. After the Program/Erase Controller pauses, the bit is `1'. The end of a Program and Erase operation can be found by polling the Program/Erase Controller Status bit can be polled. The other bits in the Status Register should not be tested until the Program/Erase Controller has completed the operation (and the Program/Erase Controller Status bit is `1'). After the Program/Erase Controller has completed its operation, the Erase Status, Program Status, VPP Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit SR6). This bit indicates that an Erase operation has been suspended, and that it is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). After a Program/Erase Suspend command is issued, the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is `0', the Program/Erase Controller is active or has completed its operation. When the bit is `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued, the Erase Suspend Status bit returns to `0'. Erase Status (Bit SR5). This bit indicates if a problem has occurred during the erasing of a Sector or Block. The Erase Status bit should be read once the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). When the Erase Status bit is `0', the memory has successfully verified that the Sector/Block has been erased correctly. When the Erase Status bit is `1', the Program/Erase Controller has applied the maximum number of pulses to the Sector/ Block and still failed to verify that the Sector/Block has been erased correctly. Once the Erase Status bit is set to `1', it can only be reset to `0' by a Clear Status Register command, or by a hardware reset. If it is set to `1', it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. Program Status (Bit SR4). This bit indicates if a problem has occurred during the programming of a byte. The Program Status bit should be read once the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). When the Program Status bit is `0', the memory has successfully verified that the byte has been programmed correctly. When the Program Status bit is `1', the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has been programmed correctly. Once the Program Status bit is set to `1', it can only be reset to `0' by a Clear Status Register command, or by a hardware reset. If it is set to `1', it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. VPP Status (Bit SR3). This bit indicates whether an invalid voltage was detected on the VPP pin at the beginning of a Program or Erase operation. The V PP pin is only sampled at the beginning of the operation. Indeterminate results can occur if VPP becomes invalid during a Program or Erase operation. Once the VPP Status bit set to `1', it can only be reset to `0' by a Clear Status Register command, or by a hardware reset. If it is set to `1', it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. Program Suspend Status (Bit SR2). This bit indicates that a Program operation has been suspended, and that it is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). After a Program/Erase Suspend command is issued, the memory may still complete the operation instead of entering the Suspend mode.
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M50FLW040A, M50FLW040B
When the Program Suspend Status bit is `0', the Program/Erase Controller is active, or has completed its operation. When the bit is `1', a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued, the Program Suspend Status bit returns to `0'. Block Protection Status (Bit SR1). The Block Protection Status bit can be used to identify if the Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to `0', no Program or Erase operations have been attempted to protected blocks Table 14. Status Register Bits
Operation Program active Program suspended Program completed successfully Program failure due to VPP Error Program failure due to Block Protection (FWH/LPC Interface only) Program failure due to cell failure Erase active Erase suspended Erase completed successfully Erase failure due to VPP Error Erase failure due to Block Protection (FWH/LPC Interface only) Erase failure due to failed cell(s) in block SR7 `0' `1 `1' `1' `1' `1' `0' `1' `1' `1' `1' `1' SR6 X(1) X(1) X(1) X(1) X(1) X(1) `0' `1' `0' `0' `0' `0' SR5 `0' `0' `0' `0' `0' `0' `0' `0' `0' `1' `1' `1' SR4 `0' `0' `0' `1' `1' `1' `0' `0' `0' `0' `0' `0' SR3 `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0' `0' SR2 `0' `1' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' SR1 `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0'
since the last Clear Status Register command or hardware reset. When the Block Protection Status bit is `1', a Program or Erase operation has been attempted on a protected block. Once it is set to `1', the Block Protection Status bit can only be reset to `0' by a Clear Status Register command or by a hardware reset. If it is set to `1', it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. Using the A/A Mux Interface, the Block Protection Status bit is always `0'. Reserved (Bit SR0). Bit 0 of the Status Register is reserved. Its value should be masked.
Note: 1. For Program operations during Erase Suspend Bit SR6 is `1', otherwise Bit SR6 is `0'.
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M50FLW040A, M50FLW040B
FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS
When the Firmware Hub Interface/Low Pin Count is selected, several additional registers can be accessed. These registers control the protection status of the Blocks, read the General Purpose Input pins and identify the memory using the manufacturer code. See Table 15. for the memory map of the Configuration Registers. The Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation, with the appropriate address (including A22=0), is all that is needed. Lock Registers The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the protection of each block: the Write Lock Bit, the Read Lock Bit and the Lock Down Bit. The Lock Registers can be read and written. Care should be taken, though, when writing. Once the Lock Down Bit is set, `1', further modifications to the Lock Register cannot be made until it is cleared again by a reset or power-up. See Table 16. for details on the bit definitions of the Lock Registers. Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Erase Command). When the Write Lock Bit is set, `1', the block is write protected - any operations that attempt to change the data in the block will fail, and the Status Register will report the error. When the Write Lock Bit is reTable 15. Configuration Register Map
Mnemonic Register Name Memory Address Default Value Access
set, `0', the block is not write protected by the Lock Register, and may be modified, unless it is write protected by some other means. If the Top Block Lock signal, TBL, is Low, VIL, then the Top Block (Block 7) is write protected, and cannot be modified. Similarly, if the Write Protect signal, WP, is Low, V IL, then the Main Blocks (Blocks 0 to 6) are write protected, and cannot be modified. After power-up, or reset, the Write Lock Bit is always set to `1' (write-protected). Read Lock. The Read Lock bit determines whether the contents of the Block can be read (in Read mode). When the Read Lock Bit is set, `1', the block is read protected - any operation that attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is reset, `0', read operations are allowed in the Block, and return the value of the data that had been programmed in the block. After power-up, or reset, the Read Lock Bit is always reset to `0' (not read-protected). Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, `1', further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset, or power-up, is required before changes to these bits can be made. When the Lock Down Bit is reset, `0', the Write Lock, Read Lock and Lock Down Bits can be changed.
Lock Registers (For details, see APPENDIX A.) GPI_REG MANU_REG Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register Manufacturer Code Register FBC0100h FBC0000h N/A 20h R R
Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9..
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M50FLW040A, M50FLW040B
Table 16. Lock Register Bit Definitions
Bit 7-3 `1' 2 Read-Lock `0' Bit Name Value Reserved Bus Read operations in this Block always return 00h. Bus read operations in this Block return the Memory Array contents. (Default value). Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a `1' is written to the Lock-Down bit it cannot be cleared to `0'; the bit is always reset to `0' following a Reset (using RP or INIT) or after power-up. Read-Lock and Write-Lock can be changed by writing new values to them. (Default value). Program and Erase operations in this Block will set an error in the Status Register. The memory contents will not be changed. (Default value). Program and Erase operations in this Block are executed and will modify the Block contents. Function (1)
`1' 1 Lock-Down `0' `1' 0 Write-Lock `0'
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-7] Lock Register (T_MINUS07_LK).
Table 17. General Purpose Inputs Register Definition
Bit 7-5 `1' 4 GPI4 `0' `1' 3 GPI3 `0' `1' 2 GPI2 `0' `1' 1 GPI1 `0' `1' 0 GPI0 `0' Input Pin GPI0 is at VIL Input Pin GPI1 is at VIL Input Pin GPI0 is at VIH Input Pin GPI2 is at VIL Input Pin GPI1 is at VIH Input Pin GPI3 is at VIL Input Pin GPI2 is at VIH Input Pin GPI4 is at VIL Input Pin GPI3 is at VIH Bit Name Value Reserved Input Pin GPI4 is at VIH Function (1)
Note: 1. Applies to the General Purpose Inputs Register (GPI-REG).
Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register The FWH/LPC General Purpose Input Register holds the state of the General Purpose Input pins, GPI0-GPI4. When this register is read, the state of these pins is returned. This register is read-only. Writing to it has no effect.
The signals on the FWH/LPC Interface General Purpose Input pins should remain constant throughout the whole Bus Read cycle. Manufacturer Code Register Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer Code for STMicroelectronics. This register is read-only. Writing to it has no effect.
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M50FLW040A, M50FLW040B
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table 18.. Table 18. Program and Erase Times
Parameter Byte Program Double Byte Program Quadruple Byte Program FWH A/A Multiplexed FWH VPP = 12V 5% VPP = 12V 5% VPP = 12V 5% Block Program VPP = VCC Sector Erase (4 KBytes)(2) VPP = 12V 5% VPP = VCC VPP = 12V 5% Block Erase (64 KBytes) VPP = VCC Chip Erase Program/Erase Suspend to Program pause(2) Program/Erase Suspend to Block Erase/ Sector Erase pause(2)
Note: 1. 2. 3. 4. 5. TA = 25C, VCC = 3.3V Sampled only, not 100% tested. Time to program two Bytes. Time to program four Bytes. Time obtained executing the Quadruple Byte Program command.
Interface
Test Condition
Min
Typ(1) 10 10(3) 10(4) 0.1(5) 0.4 0.4 0.5 0.75 1 5
Max 200 200 200 5
Unit
s
s s
s 5 4 s 5 8 s 10 s 5 30
A/A Multiplexed
VPP = 12V 5%
s s
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M50FLW040A, M50FLW040B
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 19. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VPP VESD Storage Temperature Lead Temperature during Soldering Input or Output range 2 Supply Voltage Program Voltage Electrostatic Discharge Voltage (Human Body model) 3 Parameter Min. -65 Max. 150 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
See note 1 -0.50 -0.50 -0.6 -2000
ECOPACK (R)
VCC + 0.6 4 13 2000
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. Minimum voltage may undershoot to -2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for less than 20ns during transitions. 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M50FLW040A, M50FLW040B
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 20. Operating Conditions
Symbol VCC TA Ambient Operating Temperature (Device Grade 1) 0 70 C Supply Voltage Ambient Operating Temperature (Device Grade 5) Parameter Min. 3.0 -20 Max. 3.6 85 Unit V C
Conditions summarized in Table 20., Table 21. and Table 22.. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 21. FWH/LPC Interface AC Measurement Conditions
Parameter Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Value 10 Unit pF ns V V
1.4
0.2 VCC and 0.6 VCC 0.4 VCC
Table 22. A/A Mux Interface AC Measurement Conditions
Parameter Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Value 30 Unit pF ns V V
10
0 to 3 1.5
Figure 11. FWH/LPC Interface AC Measurement I/O Waveforms
0.6 VCC 0.4 VCC 0.2 VCC Input and Output AC Testing Waveform
IO < ILO
IO > ILO
IO < ILO
Output AC Tri-state Testing Waveform
AI03404
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M50FLW040A, M50FLW040B
Figure 12. A/A Mux Interface AC Measurement I/O Waveform
3V 1.5V 0V
AI01417
Figure 13. AC Measurement Load Circuit
VDD
VPP VDD 16.7k DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI08430
Table 23. Impedance
Symbol CIN(1) CCLK(1) LPIN(2) Parameter Input Capacitance Clock Capacitance Recommended Pin Inductance Test Condition VIN = 0V VIN = 0V 3 Min Max 13 12 20 Unit pF pF nH
Note: 1. Sampled only, not 100% tested. 2. See PCI Specification. 3. TA = 25C, f = 1MHz.
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M50FLW040A, M50FLW040B
Table 24. DC Characteristics
Symbol VIH Parameter Input High Voltage A/A Mux Input Low Voltage INIT Input High Voltage INIT Input Low Voltage Input Leakage Current IC, IDx Input Leakage Current IC, IDx Input Pull Low Resistor FWH/LPC VOH Output High Voltage A/A Mux VOL ILO VPP1 VPPH VLKO(1) FWH/LPC Output Low Voltage A/A Mux Output Leakage Current VPP Voltage VPP Voltage (Fast Erase) VCC Lockout Voltage FWH4/LFRAME = 0.9VCC VPP = VCC All other inputs 0.9VCC to 0.1VCC VCC = 3.6V, f(CLK) = 33MHz FWH4/LFRAME = 0.1 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz VCC = VCC max, VPP = VCC f(CLK) = 33MHz IOUT = 0mA G = VIH, f = 6MHz Program/Erase Controller Active VPP > VCC VPP = VCC VPP = 12V 5% IOH = -500A IOH = -100A IOL = 1.5mA IOL = 1.8mA 0V VOUT VCC 3 11.4 1.8 FWH/LPC A/A Mux FWH/LPC FWH/LPC 0V VIN VCC IC, ID0, ID1, ID2, ID3(3) = VCC 20 0.9 VCC VCC - 0.4 0.1 VCC 0.45 10 3.6 12.6 2.3 Interface FWH Test Condition Min 0.5 VCC 0.7 VCC -0.5 -0.5 1.1 -0.5 Max VCC + 0.5 VCC + 0.3 0.3 VCC 0.8 VCC + 0.5 0.2 VCC 10 200 100 Unit V V V V V V
VIL VIH(INIT) VIL(INIT) ILI(2) ILI2 RIL
A A
k V V V V
A
V V V
ICC1
Supply Current (Standby)
FWH/LPC
100
A
ICC2
Supply Current (Standby)
FWH/LPC
10
mA
ICC3 ICC4 ICC5(1) IPP IPP1(1)
Supply Current (Any internal operation active) Supply Current (Read) Supply Current (Program/Erase) VPP Supply Current (Read/Standby) VPP Supply Current (Program/Erase active)
FWH/LPC A/A Mux A/A Mux
60 20 20 400 40 15
mA mA mA
A
mA mA
Note: 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs. 3. ID3 pin is RFU in LPC mode.
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M50FLW040A, M50FLW040B
Figure 14. FWH/LPC Interface Clock Waveform
tCYC tHIGH 0.6 VCC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC
AI03403
tLOW
0.4 VCC, p-to-p (minimum)
Table 25. FWH/LPC Interface Clock Characteristics
Symbol tCYC tHIGH tLOW Parameter CLK Cycle Time(1) CLK High Time CLK Low Time CLK Slew Rate peak to peak Max 4 V/ns Test Condition Min Min Min Min Value 30 11 11 1 Unit ns ns ns V/ns
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification.
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M50FLW040A, M50FLW040B
Figure 15. FWH/LPC Interface AC Signal Timing Waveforms
CLK
tCHQV FWH0-FWH3/ LAD0-LAD3 tCHQX
tCHQZ tDVCH
tCHDX
VALID tFLCH FWH4 tCHFH
START CYCLE
VALID OUTPUT DATA
FLOAT OUTPUT DATA
VALID INPUT DATA
AI09700
Table 26. FWH/LPC Interface AC Signal Timing Characteristics
Symbol PCI Symbol tval ton toff tsu th CLK to Data Out Max CLK to Active (Float to Active Delay) CLK to Inactive (Active to Float Delay) Input Set-up Time(2) Input Hold Time(2) Input Set-up time on FWH4 Input Hold time on FWH4 Min Max Min Min Min Min 11 2 28 7 0 10 5 ns ns ns ns ns ns ns Parameter Min tCHQV tCHQX(1) tCHQZ tAVCH tDVCH tCHAX tCHDX tFLCH tCHFH Value 2 Unit ns
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification. 2. Applies to all inputs except CLK and FWH4.
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M50FLW040A, M50FLW040B
Figure 16. Reset AC Waveforms
RP, INT tPLPH W, G, FWH4/LFRAME tPLRH RB tPHWL, tPHGL, tPHFL
ai08422
Table 27. Reset AC Characteristics
Symbol tPLPH tPLRH Parameter RP or INIT Reset Pulse Width Program/Erase Inactive RP or INIT Low to Reset Program/Erase Active RP or INIT Slew Rate(1) tPHFL tPHWL tPHGL RP or INIT High to FWH4/ LFRAME Low RP High to Write Enable or Output Enable Low Rising edge only FWH/LPC Interface only A/A Mux Interface only Max Min Min Min 30 50 30 50 Test Condition Min Max Value 100 100 Unit ns ns
s
mV/ns
s s
Note: 1. See Chapter 4 of the PCI Specification.
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M50FLW040A, M50FLW040B
Figure 17. A/A Mux Interface Read AC Waveforms
tAVAV A0-A10 tAVCL tCLAX RC tCHQV G tGLQV tGLQX DQ0-DQ7 tGHQZ tGHQX VALID ROW ADDR VALID COLUMN ADDR VALID tAVCH tCHAX NEXT ADDR VALID
W tPHAV RP
AI03406
Table 28. A/A Mux Interface Read AC Characteristics
Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV(1) tGLQV(1) tPHAV tGLQX tGHQZ tGHQX Parameter Read Cycle Time Row Address Valid to RC Low RC Low to Row Address Transition Column Address Valid to RC high RC High to Column Address Transition RC High to Output Valid Output Enable Low to Output Valid RP High to Row Address Valid Output Enable Low to Output Transition Output Enable High to Output Hi-Z Output Hold from Output Enable High Test Condition Min Min Min Min Min Max Max Min Min Max Min Value 250 50 50 50 50 150 50 1 0 50 0 Unit ns ns ns ns ns ns ns
s
ns ns ns
Note: 1. G may be delayed up to tCHQV - t GLQV after the rising edge of RC without impact on tCHQV.
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M50FLW040A, M50FLW040B
Figure 18. A/A Mux Interface Write AC Waveforms
Write erase or program setup A0-A10 R1 C1 tCLAX tAVCL RC tWHWL tWLWH W tVPHWH G tWHRL RB tQVVPL VPP tDVWH DQ0-DQ7 DIN1 DIN2 tWHDX VALID SRD
AI04185
Write erase confirm or valid address and data R2 tAVCH tCHAX C2
Automated erase or program delay
Read Status Register Data
Ready to write another command
tCHWH
tWHGL
Table 29. A/A Mux Interface Write AC Characteristics
Symbol tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPHWH(1) tWHGL tWHRL tQVVPL(1,2) Parameter Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Row Address Valid to RC Low RC Low to Row Address Transition Column Address Valid to RC High RC High to Column Address Transition Write Enable High to Write Enable Low RC High to Write Enable High VPP High to Write Enable High Write Enable High to Output Enable Low Write Enable High to RB Low Output Valid, RB High to VPP Low Test Condition Min Min Min Min Min Min Min Min Min Min Min Min Min Value 100 50 5 50 50 50 50 100 50 100 30 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (V PP < 3.6V).
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M50FLW040A, M50FLW040B
PACKAGE MECHANICAL
Figure 19. PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
D D1
1N
A1 A2
B1 E2 E3 E1 E e F 0.51 (.020) 1.14 (.045) D3 R CP A E2 B
D2
D2
PLCC-A
Note: Drawing is not to scale.
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M50FLW040A, M50FLW040B
Table 30. PLCC32 - 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B B1 CP D D1 D2 D3 E E1 E2 E3 e F R N 0.89 32 10.16 1.27 7.62 12.32 11.35 4.78 - 14.86 13.89 6.05 - - 0.00 - Min 3.18 1.53 0.38 0.33 0.66 Max 3.56 2.41 - 0.53 0.81 0.10 12.57 11.51 5.66 - 15.11 14.05 6.93 - - 0.13 - 0.035 32 0.400 0.050 0.300 0.485 0.447 0.188 - 0.585 0.547 0.238 - - 0.000 - Typ Min 0.125 0.060 0.015 0.013 0.026 Max 0.140 0.095 - 0.021 0.032 0.004 0.495 0.453 0.223 - 0.595 0.553 0.273 - - 0.005 - inches
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M50FLW040A, M50FLW040B
Figure 20. TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 31. TSOP32 - 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 0.050 0.950 0 0.170 0.100 Min Max 1.200 0.150 1.050 5 0.270 0.210 0.100 13.800 12.300 0.500 - 7.900 0.500 32 14.200 12.500 - 8.100 0.700 32 0.0197 0.5433 0.4843 - 0.3110 0.0197 0.0020 0.0374 0 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 5 0.0106 0.0083 0.0039 0.5591 0.4921 - 0.3189 0.0276 inches
B C CP D D1 e E L N
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M50FLW040A, M50FLW040B
Figure 21. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Table 32. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 e E L 0.500 19.800 18.300 - 9.900 0.500 0 40 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.100 20.200 18.500 - 10.100 0.700 5 40 0 1 1 - 0 0 0 0 0 0 0 Typ Min Max 0 0 0 0 0 0 1 1 - 0 0 5 inches
N
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M50FLW040A, M50FLW040B
PART NUMBERING
Table 33. Ordering Information Scheme
Example:M50FLW040 Device Type M50 = Flash Memory for PC BIOS Architecture FL = Firmware Hub/Low Pin Count Interface Operating Voltage W = VCC = 3.0 to 3.6V Device Function 040 = 4 Mbit (x8), Uniform Blocks and Sectors Array Matrix A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors Package K = PLCC32 NB = TSOP32: 8 x 14mm N = TSOP40: 10 x 20 mm Device Grade 5 = Temperature range -20 to 85 C. Device tested with standard test flow 1 = Temperature range 0 to 70 C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P = Lead-Free and RoHS compliant G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free A K 5 T P
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M50FLW040A, M50FLW040B
APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE
Table 34. M50FLW040A Block and Sector
Addresses Block Block Sector Address Sector Register Size No and Size Range No Address (KByte) Type (KByte) 7F000h7FFFFh 7E000h7EFFFh 7D000h7DFFFh 7C000h7CFFFh 7B000h7BFFFh 7A000h7AFFFh 79000h79FFFh 78000h78FFFh 64 77000h77FFFh 76000h76FFFh 75000h75FFFh 74000h74FFFh 73000h73FFFh 72000h72FFFh 71000h71FFFh 70000h70FFFh 4 4 4 4 4 4 4 4 7 (Top) 4 4 4 4 4 4 4 4 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 64 40 FBF0002 67000h67FFFh 66000h66FFFh 65000h65FFFh 64000h64FFFh 63000h63FFFh 62000h62FFFh 61000h61FFFh 60000h60FFFh 64 64 64 64 64 50000h5FFFFh 40000h4FFFFh 30000h3FFFFh 20000h2FFFFh 10000h1FFFFh 5 (Main) 4 (Main) 3 (Main) 2 (Main) 1 (Main) Block Block Sector Address Sector Register Size No and Size Range No Address (KByte) Type (KByte) 6F000h6FFFFh 6E000h6EFFFh 6D000h6DFFFh 6C000h6CFFFh 6B000h6BFFFh 6A000h6AFFFh 69000h69FFFh 68000h68FFFh 4 4 4 4 4 4 4 4 6 (Main) 4 4 4 4 4 4 4 4 23 22 21 20 19 18 17 16 FBD0002 FBC0002 FBB0002 FBA0002 FB90002 31 30 29 28 27 26 25 24 FBE0002
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M50FLW040A, M50FLW040B
Block Block Sector Address Sector Register Size No and Size Range No Address (KByte) Type (KByte) 0F000h0FFFFh 0E000h0EFFFh 0D000h0DFFFh 0C000h0CFFFh 0B000h0BFFFh 0A000h0AFFFh 09000h09FFFh 08000h08FFFh 64 07000h07FFFh 06000h06FFFh 05000h05FFFh 04000h04FFFh 03000h03FFFh 02000h02FFFh 01000h01FFFh 00000h00FFFh 4 4 4 4 4 4 4 4 0 (Main) 4 4 4 4 4 4 4 4 7 64 6 5 4 3 2 1 0 77000h77FFFh 76000h76FFFh 75000h75FFFh 74000h74FFFh 73000h73FFFh 72000h72FFFh 71000h71FFFh 70000h70FFFh 64 64 64 64 64 60000h6 6FFFFh (Main) 50000h5 5FFFFh (Main) 40000h4FFFFh 30000h3FFFFh 20000h2FFFFh 4 (Main) 3 (Main) 2 (Main) 15 14 13 12 11 10 9 8 FB80002
Table 35. M50FLW040B Block and Sector
Addresses Block Block Sector Address Sector Register Size No and Size Range No Address (KByte) Type (KByte) 7F000h7FFFFh 7E000h7EFFFh 7D000h7DFFFh 7C000h7CFFFh 7B000h7BFFFh 7A000h7AFFFh 79000h79FFFh 78000h78FFFh 4 4 4 4 4 4 4 4 7 (Top) 4 4 4 4 4 4 4 4 39 38 37 36 35 34 33 32 FBE0002 FBD0002 FBC0002 FBB0002 FBA0002 47 46 45 44 43 42 41 40 FBF0002
Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9..
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M50FLW040A, M50FLW040B
Block Block Sector Address Sector Register Size No and Size Range No Address (KByte) Type (KByte) 1F000h1FFFFh 1E000h1EFFFh 1D000h1DFFFh 1C000h1CFFFh 1B000h1BFFFh 1A000h1AFFFh 19000h19FFFh 18000h18FFFh 64 17000h17FFFh 16000h16FFFh 15000h15FFFh 14000h14FFFh 13000h13FFFh 12000h12FFFh 11000h11FFFh 10000h10FFFh 4 4 4 4 4 4 4 4 1 (Main) 4 4 4 4 4 4 4 4 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 FB90002 64 07000h07FFFh 06000h06FFFh 05000h05FFFh 04000h04FFFh 03000h03FFFh 02000h02FFFh 01000h01FFFh 00000h00FFFh Block Block Sector Address Sector Register Size No and Size Range No Address (KByte) Type (KByte) 0F000h0FFFFh 0E000h0EFFFh 0D000h0DFFFh 0C000h0CFFFh 0B000h0BFFFh 0A000h0AFFFh 09000h09FFFh 08000h08FFFh 4 4 4 4 4 4 4 4 0 (Main) 4 4 4 4 4 4 4 4 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 FB80002
Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9..
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M50FLW040A, M50FLW040B
APPENDIX B. FLOWCHARTS AND PSEUDO CODES
Figure 22. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
Write Address and Data
Program command: - Write 40h or 10h - Write Address and Data (memory enters read status state after the Program command)
NO Read Status Register Suspend NO YES Suspend Loop
do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES FWH/LPC Interface Only SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
If SR3 = 1, - Enter the "VPP invalid" error handler
NO
Program Error (1, 2)
If SR4 = 1, - Enter the "Program error" error handler
NO
Program to Protected Block Error (1, 2)
If SR1 = 1, - Enter the "Program to protected block" error handler
AI08425B
Note: 1. A Status check of SR1 (Protected Block), SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M50FLW040A, M50FLW040B
Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only)
Start
Write 40h or 10h
Write Start Address and 2/4 Data Bytes (3)
Double/Quadruple Byte Program command: - write 40h or 10h - write Start Address and 2/4 Data Bytes (3) (memory enters read status state after the Double/Quadruple Byte Program command)
NO Read Status Register Suspend NO YES Suspend Loop
do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
If SR3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If SR4 = 1, Program error: - error handler
NO
Program to Protected Block Error (1, 2)
If SR1 = 1, Program to protected block error: - error handler
AI08423B
Note: 1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. A0 and/or A1 are treated as Don't Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte Program). For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even address, and the second at the odd address. For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address that has A1-A0 at 11.
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M50FLW040A, M50FLW040B
Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
Quadruple Byte Program command: - write 30h - write Address 1 & Data 1 (3) - write Address 2 & Data 2 (3) - write Address 3 & Data 3 (3) - write Address 4 & Data 4 (3) (memory enters read status state after the Quadruple Byte Program command)
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3) do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
NO Read Status Register Suspend NO YES Suspend Loop
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES End
NO
VPP Invalid Error (1, 2)
If SR3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If SR4 = 1, Program error: - error handler
AI08437B
Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.
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M50FLW040A, M50FLW040B
Figure 25. Program Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend command: - write B0h - write 70h do: - read Status Register
Read Status Register
SR7 = 1 YES SR2 = 1 YES Write a read Command
NO
while SR7 = 0
NO
Program Complete
If SR2 = 0 Program completed
Read data from another address
Write D0h
Write FFh
Program Continues
Read Data
Program/Erase Resume command: - write D0h to resume the program - if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).
AI08426B
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used.
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M50FLW040A, M50FLW040B
Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 80h
Chip Erase command: - write 80h - write 10h (memory enters read Status Register after the Chip Erase command)
Write 10h do: - read Status Register
Read Status Register
SR7 = 1
NO
while SR7 = 0
YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES End
AI08428B
NO
VPP Invalid Error (1)
If SR3 = 1, VPP invalid error: - error handler
NO
Command Sequence Error (1)
If SR4, SR5 = 1, Command sequence error: - error handler
NO
Erase Error (1)
If SR5 = 1, Erase error: - error handler
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M50FLW040A, M50FLW040B
Figure 27. Sector/Block Erase Flowchart and Pseudo Code
Start
Write 20h/32h
Write Block Address and D0h
Block Erase command: - Write 20h/32h - Write block Address and D0h (memory enters read Status Register after the Block Erase command)
Read Status Register
NO Suspend
YES
do: - Read Status Register - If SR7=0 and a Program/Erase Suspend command has been executed - SR7 is set to 1 - Enter suspend program loop
SR7 = 1
NO
Suspend Loop
YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES FWH/LPC Interface Only SR1 = 0 YES End
AI08424B
NO
VPP Invalid Error (1)
If SR3 = 1, - Enter the "VPP invalid" error handler
NO
Command Sequence Error (1)
If SR4, SR5 = 1, - Enter the "Command sequence"error handler
NO
Erase Error (1)
If SR5 = 1, - Enter the "Erase Error" error handler
NO
Erase to Protected Block Error (1)
If SR1 = 1, - Enter the "Erase to protected block" error handler
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M50FLW040A, M50FLW040B
Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend command: - write B0h - write 70h do: - read Status Register
Read Status Register
SR7 = 1 YES SR6 = 1 YES
NO
while SR7 = 0
NO
Erase Complete
If SR6 = 0, Erase completed
Read data from another block/sector or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume erase - if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).
AI08429B
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M50FLW040A, M50FLW040B
REVISION HISTORY
Table 36. Document Revision History
Date 23-Jun-2003 04-Jul-2003 28-Jul-2003 08-Oct-2003 07-Nov-2003 18-Feb-2004 18-May-2004 18-Aug-2004 Version 1.0 2.0 2.1 2.2 2.3 3.0 4.0 5.0 First Issue VIH(INIT) min parameter modified in Table 24., DC Characteristics. Document status promoted from Target Specification to Product Preview Document renamed to M50FLW040A, M50FLW040B Block types removed from the Block and Sector Address tables Document promoted to Preliminary Data Wording in the textual discriptions revised throughout the document. TSOP32 package added. Updates to Tables 8, 9, 12, 13, 14, 15, 19, 26, 34 and 35; and to Figures 15, and 22 to 28 Pins 2 and 5 of the TSOP32 Connections illustration corrected Revision Details
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M50FLW040A, M50FLW040B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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